1. Field of the Invention
The present invention relates to data modulating/demodulating method and apparatus, and more particularly, to a method and apparatus for suppressing a direct-current (DC) component of coded sequence with no additional bit for suppressing a DC component, and for decoding the coded sequence.
2. Description of the Related Art
In these days, an optical recording medium is widely and successfully used for storing various information such as video and audio signals. An optical recording medium is classified into two types: ‘read-only’ one such as CD-ROM and DVD-ROM, and ‘writable’ type such as CD-R, DVD-R, CD-R/W, and DVD-RAM.
When data is written to a conventional writable optical recording medium, the data is modulated into a code matching the recording medium prior to the recording in order to stabilize a servo mechanism in data recording and to stabilize a reproducing clock in data reproduction. Such modulation must satisfy the following constraints: code efficiency is high; a reproducing clock is stable; jitter margin for detecting data stably is ensured; a DC component or digital sum value (DSV) is minimized enough to stabilize data detection and tracking servo; no or the least error propagation arises; and code words have fewer bits as possible as they can.
EFM (Eight-to-Fourteen Modulation) is used for CD series and EFM+(called ‘EFM plus’) is used for DVD series. Owing to these two modulations, data having high-frequency components is converted to lower frequency signals, which will induce stabilization of servo mechanism.
In EFM, one byte, namely, 8 bits are coded to 17-bit symbol data including 3-bit merging bits, and, in EFM+, 8 bits are coded to a 16-bit modulated word depending upon a previous state. The coded data is then converted to NRZI (Non-Return to Zero Inverted) unit which will be written to a writable disk in marks and edges. The distance between successive edges is limited by the rule of RLL (Run Length Limitation), generically designated as RLL(d,k), which means having constraints that at least d ‘zeros’ are recorded between successive ‘ones’, and that no more than k ‘zeros’ are recorded between successive ‘ones’. The first constraint arises to obviate intersymbol interference occurring because of pulse crowding of the reproduced ones, which mean transitions, namely ones when a series of ‘ones’ are contiguously recorded. The second constraint arises to ensure recovering a clock from the reproduced data by locking a PLL to the reproduced transitions.
For example, in RLL (2,10) used for DVD series, at least two ‘zeros’ are placed between recorded ‘ones’, and no more than ten contiguous ‘zeros’ are placed between recorded ‘ones’. Therefore, after NRZI conversion, minimum run length time is (d+1)T and maximum run length time is (k+1)T where T is a channel bit interval. That is, for the example of a (2,10) code, the run length time ranges from 3T to 11T inclusive.
In general, data modulation may use a fixed block scheme in which source data is one-to-one mapped to corresponding modulated data with reference to a conversion table. For this mapping, there is a single conversion table for CD series containing 256 (0 to 255) 16-bit code words whereas there are four sets of main conversion tables and four sets of sub-tables for DVD series. Each main table contains 256 16-bit code words and each sub-table contains 88 (0 to 87) 16-bit code words. However, in the fixed block scheme, the RLL constraints may be violated between two consecutive bytes under a given code rate even though each byte satisfies the RLL constraints. If the RLL constraints are violated between two successive bytes, one bit must be inserted therebetween. Moreover, one additional bit is added for DC balance. This additional bit for the DC balance demands another one bit to satisfy the given RLL constraints. Therefore, a total of three bits must be inserted if the given RLL constraints are violated between two successive bytes.
As described above, the fixed block scheme has an advantage of no conversion error because a source data is one-to-one mapped to the corresponding modulated data, whereas it has a drawback in that the recording density is somewhat limited because of a merging bit and additional bits which are necessary when the given RLL constraints are violated between two consecutive bytes.
In the modulation for DVD series, no need for additional bits arises because a previous mapping state is considered at the present mapping process. This modulation is called a ‘look-ahead’ scheme in comparison with the fixed block scheme. However, there are problems in that mapping algorithm is complicated and many tables are required. The look-ahead scheme is superior to the fixed block scheme in increasing storage capacity. In the look-ahead scheme, the modulation of a current data (symbol) is dependent on next data or previous data occasionally. The look-ahead scheme needs a simple algorithm and hardware and it requires only 2 bits for DC balance as well. Therefore, it can ensure higher storage capacity of a recording medium than the fixed block scheme.
However, the look-ahead scheme has a drawback in that if an error occurs in a certain data, it propagates to subsequent data because the modulation of a current data depends upon the next or previous data.
For a high-density writable optical recording medium, new modulating methods are being demanded to ensure stable jitter margin and to increase storage capacity. The new modulating methods have common tendencies in that the code rate is 2/3 to convert an 8-bit source data to a 12-bit code data and (1, 7) or (1, 8) code is used. In this case, DSV is minimized to stabilize data reproduction and servo mechanism.
When data is recorded onto a recording medium or transmitted through a transmission line, the data is modulated into a coded sequence matching the recording medium or the transmission line. If the coded sequence resulting from the modulation contains a DC component, a variety of error signals such as tracking errors generated in control of a servo mechanism of a disk drive become prone to variations. As a result, jitters of the error signals are generated severely.
Therefore, it is desirable to suppress low-frequency components of the coded sequence in order to make a servo irresponsive to low-frequency components. In order to prevent the modulated sequence from containing a DC component, control of DSV has been proposed. The DSV is an indicator of a DC component contained in a train of sequences, and it is a total found by adding up the values of a train of bits, wherein the values +1 and −1 are assigned to ‘1’ and ‘0’ in the train respectively, which results in after the NRZI modulation of a train of channel bits. For example, if a train of bits is “1001000” after the modulation, it is converted to “1110000” by the NRZI modulation. For this sequence, the DSV varies to 1, 2, 3, 2, 1, 0, and −1 sequentially bit by bit.
A substantially constant DSV means that the frequency spectrum of the signal does not comprise frequency components in the low frequency zone. The DSV control is accomplished by calculating a DSV of a train of encoded bits after an RLL(d,k) modulation for a predetermined period of time and inserting a predetermined number of DSV control bits into the train of encoded bits. In order to improve the code efficiency, it is desirable to reduce the number of DSV control bits to a smallest possible value.